In many applications, it is often desirable to be able to fabricate different types of devices on the same wafer. For instance, one might want to produce logic and memory devices on the same chip. Different devices, however, have different requirements. For instance, logic devices might require a different supply voltage than a memory device, and with memory devices, such as static random access memory (SRAM), controlling leakage current is an important consideration. Thus being able to fabricate different types of devices on the same chip presents some unique challenges.
The use of III-V semiconductor materials (i.e., materials that include at least one group III element and at least one group V element) has been proposed for future generations of metal oxide semiconductor field-effect transistor (MOSFET) devices. This is due to their favorable electron transport properties. See, for example, del Alamo et al., “The Prospects for 10 nm III-V CMOS,” VLSI Technology Systems and Applications (VLSI-TSA), 2010 International Symposium, pgs. 166-167 (April 2010) (hereinafter “del Alamo”). It is however difficult to implement a III-V semiconductor material in the context of a hybrid device design, i.e., one wherein multiple types of devices are being fabricated on the same chip. Take for instance the example above of a chip having both logic and memory devices. While use of a III-V material as the channel material for a logic device is rather straightforward, in order to meet the low leakage current requirements for the memory devices, the III-V material would have to be much more dense. Thus finding a III-V material to meet the unique specifications of these different device types is a challenge.
Thus, techniques that permit implementation of a III-V semiconductor material in the context of fabricating hybrid device designs on the same chip would be desirable.